IC chips are well known in the art and are in a continual state of development. Such chips may contain thousands of microscopic circuit elements and transistors, resistors, etc. Such elements are interconnected within the IC chip in various circuit configurations, and have input/output circuit leads. The chips typically are mounted in chip carriers with these input/output leads connected to conductive areas or pads which may be located about the chip carrier outer periphery or in various patterns across the bottom surface such as on land grid arrays.
The various chip circuits are desirably tested prior to installation in an electronic device to insure proper functioning thereof. Replacement of a faulty chip following installation in a device is both time-consuming and expensive. Accordingly, defective chips must be discovered and discarded if at all possible, prior to installation. Testing is thus seen to be a mandatory preliminary step, particularly as the increasing complexity of IC chips results in a high-percentage failure rate. This testing normally includes circuit testing after the chip is mounted in the chip carrier by contacting the pads on the carrier with suitable test apparatus. Thus the testing and apparatus referred to hereinafter is discussed herein in terms of effecting testing contacts with the chip carrier.
The prior art has employed chip testers using metal or elastomers for conducting signals from a printed circuit trace to an IC chip carrier pad of the chip to be tested. Such elastomers however have a very limited working life and are readily damaged or deteriorate following several test cycles, requiring replacement. Obviously the testing process becomes extremely expensive when thousands of chips are tested daily on a regular basis.
Examples of prior art utilization of such conductive elastomers for use in connectors comprise Buchoff et al. U.S. Pat. No. 3,971,610 of Jul. 27, 1976 and Fahling U.S. Pat. No. 4,360,858 of Nov. 23, 1982.
In accordance with this invention at least one connector comprising a wadded conductive wire button in combination with a conductive plunger is mounted in an apertured insulator board for establishing electrical contact between the pads of a chip and the circuit traces of a PC test board.
The wadded wire adapted to engage the trace of a PC board is resiliently deformable when compressed between the trace and the base of the plunger. The plunger distal end projects from the insulator opening in which disposed for purposes of effecting substantially a point contact with a chip carrier pad by the resilient force of the button.
The use of such wadded wire conductor buttons per se in mounting boards for effecting electrical connections is shown in the prior patent art as in Smolley U.S. Pat. Nos. 4,574,331 of Mar. 4, 1986 and 4,581,679 of Apr. 8, 1986. Also, the use of such wadded wire buttons in testing apparatus is disclosed in Smolley U.S. Pat. No. 4,733,172 of Mar. 22, 1988 in which opposed ends of the disclosed buttons are seen to engage a chip pad and a contact area of a test circuit board.
It has been found however that in the course of relative movement between an end portion of a wadded contact button protruding from a carrier board and a trace of a PC board in the course of effecting repeated desired button-pad location and contact, the wire of the button tends to unravel and cause shorting with an adjacent circuit. Such unraveling also results in non-uniform button-conductor contacts and resultant conductivity inconsistency. Thus it has been found that engagement with loose wire ends of a button contact with an engaging conductive surface will result in undesired increased resistance to current passage.
It is an object of this invention therefore to provide a chip tester employing a wadded wire contact able to effect in excess of 25,000 testing cycles without the need for contact replacement. This is made possible by utilizing in conjunction with such button contacts a plunger having an enlarged base. The plunger engages an associated button disposed within a carrier board at its inner end, and engages a pad of a chip carrier by means of the rounded end of a needle-like projection extending exteriorly of a carrier board in which the plunger is mounted. The latter pad plunger contact effects negligible wear on the plunger and the resiliency of the wire button contact assures desired long extended life of the button-plunger contact combination. The button-engaging plunger may assume other configurations for effecting a low resistance contact as for instance a rounded dome-like projecting portion.
In the various button plunger arrangements care must be taken to design the button-receiving aperture of the button board or carrier so as to allow the button to freely compress and expand in the normal course of urging the plunger contact portion into engagement with a conductive pad or the like. Impairment of the spring action of the wadded wire buttons would adversely affect the positioning of the button ends causing variances in the compressive engagement of the button with resultant unpredictability of the resistance through the resulting button interface.
It is another object of this invention to provide a chip tester of low inductance particularly adapted for high frequency applications, having been successfully tested at 1.5 gigahertz. This is made possible by the low resistance and low inductive electrical path provided by each of the tester contacts hereinafter disclosed.
It is a further object of this invention to provide a button-plunger contact assembly which is particularly suited for rapid connect-disconnect operation and where high signal propagation is desired.
Thus in accordance with one embodiment of this invention a chip tester is provided comprising superimposed apertured insulator boards. In a first board projecting plungers are mounted for effecting substantially point contact with the pads of carriers of IC chips to be tested. In a second insulator board, wadded wire contact buttons are mounted in the apertures thereof and the opposed ends thereof project from opposed surfaces of the board in which the buttons are mounted. The buttons may thus project into the apertures of the overlying plunger board and resiliently bias the terminal plunger contact ends exteriorly of the first board.
The plunger ends may effect substantially point contacts with the pads of a chip carrier to be tested, and the button end portion projecting from the bottom of the second insulator board may effect desired contact with the trace of a test PC board.
With appropriate assembly techniques or sequences, the provided plunger-button contact portions may be disposed in the apertures of a single board and work to equal advantage.
In a modified plunger-button construction particularly adapted for quick make-and-break of electrical contacts, a wadded wire button contact is disposed in an aperture of an insulator housing and engages contact plungers at opposed button ends. The plungers have pin-like pad-engaging terminal contacts which are resiliently biased by the button contacts to project from the housing apertures in which disposed. The opposed plunger contacts may thus readily effect contacts with the contact pads or traces of PC boards or chips to be interconnected when said pads or traces are urged against the resiliently biased plungers, as will hereinafter be described in greater detail.
In the various button and button board embodiments hereafter described, the buttons are desirably retained in button board openings in such manner as to ensure the necessary button resiliency utilized in the normal course of button operation.